Semiconductor devices such integrated circuit chips are often packaged on a substrate, wire bonds attached to contact pads on the integrated circuit chip and a plastic housing secured to the substrate and/or chip. Packaging often takes the lead frame input and output routings from about 6-7 mil pitch and opens them up to a 20 mil pitch or more. The package makes chip testing easy because the easiest way to make contact with the chip is through wire bonding. If the chip fails the testing, the entire package must be thrown away. The situation becomes more problematic with respect to multi-chip modules containing a set of chips. After packaging, if one chip is bad, the entire chip set and package must be thrown away.
Therefore, it is desirable to do burn-in testing on bare-die chips before they are packaged. To date there are a variety of ways to make a temporary connection to a bare-die chip. However, most of these approaches test a single chip at a time.
Attempts to test integrated circuits at the wafer level becomes even more complicated. At the wafer level (i.e., before the individual chips are cut from the wafer), there may be 500 dies to test. This requires 500 times the power and 500 times the amount of electrical routing. In order to test all of the dies at the same time it becomes necessary to utilize a multi-layer substrate having a plurality of circuits built on top of each other to achieve the dense electrical routing requirements necessary for testing at the wafer level. However, since a plurality of circuits are built on top of each other, such multi-layer substrates having a nonplanar top surface. The top surface of the multi-layer substrate may also become further warped during the fabrication process of the substrate. A direct connection between the flat surface of the wafer and the nonplanar top surface of the multi-layer substrate cannot be made due to the uneven topography of the multi-layer substrate.
The present invention provides advantages and alternatives over the prior art.